DRAM (dynamic random access memory) is a RAM in need of refreshing, and is a memory which stores data based on presence or absence of electric charge on capacitors. Data stored in DRAM expires with the elapse of time due to leakage current from the capacitors. It is therefore necessary to read out the data at predetermined time intervals, and to write (restore) them again. This is referred to as refreshing. DARM can be realized with a memory cell area smaller than that of SRAM (static random access memory), and thereby can be obtained as a large-capacity, economic memory.
SRAM is a RAM in no need of refreshing, of which memory cell being composed of a flipflop, and information once written therein will never be lost until a power source is disconnected. SRAM is simple to use and is ready to attain high-speed performance, because only a simple operational timing control is necessary, without needing refreshing.
Pseudo SRAM has memory cells based on a DRAM structure, and has, incorporated therein, a refresh circuit for automatic refreshing. Unlike DRAM, the control thereof is simple, because there is no need of externally controlling the refreshing. External interface of which is similar to that of SRAM.
It is not possible to know timing of the refreshing of SRAM from the external, because SRAM is internally refreshed in an automatic manner. During the refreshing, data cannot be read out from the memory cells. This results in an operation such that, if a read command is entered from the external during the refreshing, the reading can start only after the refreshing comes to the end. Access time (time required before data output) during the reading therefore amounts as much as a sum of the refreshing time and reading time for the worst case. It is therefore an important factor to shorten the refreshing time in view of shortening the access time.